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? semiconductor components industries, llc, 2014 april, 2014 ? rev. p2 1 publication order number: NCP6336/d NCP6336 product preview configurable 5.0 a step down converter - transient load helper the NCP6336 is a synchronous buck converter optimized to supply the different sub systems of portable applications powered by one cell li?ion or three cell alkaline/nicd/nimh batteries. the device is able to deliver up to 5.0 a, with programmable output voltage from 0.6 v to 1.5 v. it can share the same output rail with another dc?to?dc converter and works as a transient load helper. operation at a 3 mhz switching frequency allows the use of small components. synchronous rectification and automatic pwm/pfm transitions improve overall solution efficiency. the NCP6336 is in a space saving, low profile 2.0 x 1.6 mm csp?20 package. features ? input voltage range from 2.3 v to 5.5 v: battery and 5 v rail powered applications ? programmable output voltage: 0.6 v to 1.5 v in 10 mv steps ? 3 mhz switching frequency with on chip oscillator ? uses 330 nh inductor and 47 f capacitors for optimized footprint and solution thickness ? pfm/pwm operation for optimum increased efficiency ? low 35 a quiescent current ? i 2 c control interface with interrupt and dynamic voltage scaling support ? enable pins, power good / fail signaling ? thermal protections and temperature management ? transient load helper: share the same rail with another rail ? small 2.0 x 1.6 mm / 0.4 mm pitch csp package ? these are pb?free devices typical applications ? smartphones ? tablets 330 nh 47 uf processor core NCP6336 i c thermal protection processor i c control interface operating mode control output monitoring voltage selection interrupt power fail dcdc 5.0 a supply input dcdc 3 mhz controller sense enable control input 4.7 uf sda scl agnd pgnd intb pgnd pg vsel en core sw pvin pgnd fb d2 e1 b4 a2 a1 b3 b2 b1 a3 d3 d4 e3 e4 c1 c2 c3 c4 a4 e2 d1 avin figure 1. typical application circuit this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. wlcsp20 case 568ag marking diagram http://onsemi.com see detailed ordering and shipping information on page 29 o f this data sheet. ordering information x = p: prototype = blank: production a = assembly location wl = wafer lot y = year ww = work week = pb?free package pb?free indicator, g or microdot ( ), may or may not be present 4 pvin avin sw sw pvin pgnd pgnd intb* scl en pvin pgnd pgnd sda pgnd pg* vsel sw sw pgnd fb agnd 3 2 1 e d c b a pin out (top view) *optional 6336x awlyww
NCP6336 http://onsemi.com 2 figure 2. simplified block diagram core thermal protection output voltage monitoring operating mode control logic control interrupt i2c 3 mhz dc?dc converter controller sense en agnd pg vsel intb scl sda sw sw sw sw pgnd pgnd pgnd pgnd fb pvin pvin pvin 5.0 a dc?dc analog ground enable control input voltage selection interrupt output (optional) processor i 2 c control interface power good (optional) power switch power feedback avin supply input input node ground
NCP6336 http://onsemi.com 3 4 pvin avin sw sw pvin pgnd pgnd intb* scl en pvin pgnd pgnd sda pgnd pg* vsel sw sw pgnd fb agnd 3 2 1 e d c b a figure 3. pin out (top view) *optional pin function description pin name type description reference d1 avin analog input analog supply. this pin is the device analog and digital supply. could be connected directly to the vin plane just next to the 4.7 f pvin capacitor or to a dedicated 1.0 f ceramic capacitor. b4 agnd analog ground analog ground. analog and digital modules ground. must be connected to the sys- tem ground. control and serial interface a2 en digital input enable control. active high will enable the part. there is an internal pull down resist- or on this pin. a1 vsel digital input output voltage / mode selection. the level determines which of two programmable configurations to utilize (operating mode / output voltage). there is an internal pull down resistor on this pin; could be left open if not used. a3 scl digital input i 2 c interface clock line. there is an internal pull down resistor on this pin; could be left open if not used b1 sda digital input/output i 2 c interface bi?directional data line. there is an internal pull down resistor on this pin; could be left open if not used b3 pgnd pg digital output analog ground power good open drain output. if not used has to be connected to ground plane b2 pgnd intb digital output analog ground interrupt open drain output. if not used has to be connected to ground plane dc to dc converter d2, e1, e2 pvin power input switch supply. these pins must be decoupled to ground by a 4.7 f ceramic capa- citor. it should be placed as close as possible to these pins. all pins must be used with short heavy connections. d3, d4, e3, e4 sw power output switch node. these pins supply drive power to the inductor. typical application uses 0.33 h inductor; refer to application section for more information. all pins must be used with short heavy connections. c1, c2, c3, c4 pgnd power ground switch ground. this pin is the power ground and carries the high switching current. high quality ground must be provided to prevent noise spikes. to avoid high?density current flow in a limited pcb track, a local ground plane that connects all pgnd pins together is recommended. analog and power grounds should only be connected together in one location with a trace. a4 fb analog input feedback voltage input. must be connected to the output capacitor positive termin- al with a trace, not to a plane. this is the positive input to the error amplifier.
NCP6336 http://onsemi.com 4 maximum ratings rating symbol value unit analog and power pins: avin, pvin, sw, pg, intb, fb (note 1) v a ?0.3 to + 6.0 v digital pins: scl, sda, en, vsel, pin: input voltage input current v dg i dg ?0.3 to v a + 0.3 6.0 10 v ma human body model (hbm) esd rating (note 2) esd hbm 2500 v charged device model (cdm) esd rating (note 2) esd cbm 1250 v latch up current: (note 3) digital pins all other pins i lu 10 100 ma storage temperature range t stg ?65 to +150 c maximum junction temperature t jmax ?40 to +150 c moisture sensitivity (note 4) msl level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 2. this device series contains esd protection and passes the following ratings: human body model (hbm) 2.5 kv per jedec standard: jesd22?a114. charged device model (cdm) 1250 v per jedec standard: jesd22?c101 class iv 3. latch up current per jedec standard: jesd78 class ii. 4. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a. operating conditions symbol parameter conditions min typ max unit av in, pv in power supply 2.3 5.5 v t a ambient temperature range ?40 25 +85 c t j junction temperature range (note 6) ?40 25 +125 c r ja thermal resistance junction to ambient (note 7) csp?20 on demo?board ? 55 ? c/w p d power dissipation rating (note 8) t a 85 c ? 727 ? mw p d power dissipation rating (note 8) t a = 65 c ? 1090 ? mw l inductor for dc to dc converter (note 5) 0.26 0.33 0.56 h co output capacitor for dc to dc converter (note 5) 30 ? 150 f cin input capacitor for dc to dc converter (note 5) 4.7 ? ? f functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 5. including de?ratings (refer to the application information section of this document for further details) 6. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 7. the r ja is dependent of the pcb heat dissipation. board used to drive this data was a NCP6336evb board. it is a multilayer board with 1?once internal power and ground planes and 2?once copper traces on top and bottom of the board. 8. the maximum power dissipation (p d ) is dependent by input voltage, maximum output current and external components selected. r ja 125 t a p d
NCP6336 http://onsemi.com 5 electrical characteristics (notes 10 and 11) min and max limits apply for t a = ?40 c to +85 c, avin = pvin = 3.6 v and default configuration, unless otherwise specified. typical values are referenced to t a = +25 c, avin = pvin = 3.6 v and default configuration, unless otherwise specified. symbol parameter conditions min typ max unit supply current: pins avin ? pvinx i q pwm operating quiescent current pwm dcdc active in forced pwm no load ? 15 25 ma i q pfm operating quiescent current pfm dcdc active in auto mode no load ? minimal switching ? 35 70 a i sleep product sleep mode current en high, dcdc off or en low and (vsel high or sleep_mode high) v in = 2.5 v to 5.5 v ? 7 15 a i off product in off mode en, vsel and sleep_mode low v in = 2.5 v to 5.5 v ? 0.8 5 a dc to dc converter pv in input voltage range 2.3 ? 5.5 v i outmax maximum output current ipeak[1..0] = 00 (note 12) 3.5 ? ? a ipeak[1..0] = 01 (note 12) 4.0 ? ? ipeak[1..0] = 10 (note 12) 4.5 ? ? ipeak[1..0] = 11 (note 12) 5.0 ? ? vout output voltage dc error forced pwm mode, no load ?1 ? 1 % forced pwm mode, v in range, i out up to i outmax (note 12) ?1 ? 1 auto mode, v in range, i out up to i outmax (note 12) ?1 ? 2 f sw switching frequency 2.70 3 3.30 mhz r onhs p?channel mosfet on resistance from pvin to sw v in = 5.0 v ? 23 40 m r onls n?channel mosfet on resistance from sw to pgnd v in = 5.0 v ? 12 20 m i pk peak inductor current open loop ? ipeak[1..0] = 00 (note 12) ? 5.2 ? a open loop ? ipeak[1..0] = 01 (note 12) ? 5.8 ? open loop ? ipeak[1..0] = 10 (note 12) ? 6.2 ? open loop ? ipeak[1..0] = 11 6.1 6.8 7.8 dc load load regulation i out from 0 a to i outmax (note 12) forced pwm mode ? ?0.2 ? %/a dc line line regulation i out = 3 a 2.3 v v in 5.5 v (note 12) forced pwm mode ? 0 ? % ac load transient load response tr = ts = 100 ns load step 1.2 a (note 12) ? 40 ? mv d maximum duty cycle ? 100 ? % t start turn on time time from en transitions from low to high to 90% of output voltage (delay[2..0] = 000b) ? 90 110 s r disdcdc dcdc active output discharge v out = 1.15 v ? 25 35 9. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. p rod- uct performance may not be indicated by the electrical characteristics if operated under different conditions. 10. refer to the application information section of this data sheet for more details. 11. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 12. guaranteed by design and characterized.
NCP6336 http://onsemi.com 6 electrical characteristics (notes 10 and 11) min and max limits apply for t a = ?40 c to +85 c, avin = pvin = 3.6 v and default configuration, unless otherwise specified. typical values are referenced to t a = +25 c, avin = pvin = 3.6 v and default configuration, unless otherwise specified. symbol unit max typ min conditions parameter en, vsel v ih high input voltage 1.05 ? ? v v il low input voltage ? ? 0.4 v t ftr digital input x filter en, vsel rising and falling dbn_time = 01 (note 12) 0.5 ? 4.5 s i pd digital input x pull?down (input bias current) ? 0.05 1.00 a pg (optional) v pgl power good threshold falling edge as a percentage of nominal output voltage 86 90 94 % v pghys power good hysteresis 0 3 5 % t rt power good reaction time for dcdc falling (note 12) rising (note 12) ? 3.5 3.5 ? ? 14 s v pgl power good low output voltage i pg = 5 ma ? ? 0.2 v pg lk power good leakage current 3.6 v at pg pin when power good valid ? ? 100 na v pgh power good high output voltage open drain ? ? 5.5 v intb (optional) v intbl intb low output voltage i int = 5 ma 0 ? 0.2 v v intbh intb high output voltage open drain ? ? 5.5 v intb lk intb leakage current 3.6 v at intb pin when intb valid ? ? 100 na i 2 c v i2cint high level at scl/sca line 1.7 ? 5.0 v v i2cil scl, sda low input voltage scl, sda pin (note 11, 12) ? ? 0.5 v v i2cih scl, sda high input voltage scl, sda pin (note 11, 12) 0.8 * v i2cint ? ? v v i2col sda low output voltage i sink = 3 ma (note 12) ? ? 0.4 v f scl i 2 c clock frequency (note 12) ? ? 3.4 mhz total device v uvlo under voltage lockout v in falling ? ? 2.3 v v uvloh under voltage lockout hysteresis v in rising 60 ? 200 mv t sd thermal shut down protection ? 150 ? c t warning warning rising edge ? 135 ? c t pwth pre ? warning threshold i 2 c default value ? 105 ? c t sdh thermal shut down hysteresis ? 30 ? c t warningh thermal warning hysteresis ? 15 ? c t pwth h thermal pre?warning hysteresis ? 6 ? c 9. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. p rod- uct performance may not be indicated by the electrical characteristics if operated under different conditions. 10. refer to the application information section of this data sheet for more details. 11. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 12. guaranteed by design and characterized. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
NCP6336 http://onsemi.com 7 typical operating characteristics av in = pv in = 3.6 v, t j = +25 c, dcdc = 1.15 v, ipeak = 3.9 a (unless otherwise noted). l = 0.33 h pife25201b ? c out = 47 f 0603, c in = 4.7 f 0603 figure 4. efficiency vs i load and v in v out = 1.50 v, spm5030 inductor figure 5. efficiency vs i load and temperature v out = 1.50 v, spm5030 inductor figure 6. efficiency vs i load and v in v out = 1.15 v, spm5030 inductor figure 7. efficiency vs i load and temperature v out = 1.15 v, spm5030 inductor figure 8. efficiency vs i load and v in v out = 0.60 v, spm5030 inductor figure 9. efficiency vs i load and temperature v out = 0.60 v, spm5030 inductor
NCP6336 http://onsemi.com 8 typical operating characteristics av in = pv in = 3.6 v, t j = +25 c, dcdc = 1.15 v, ipeak = 3.9 a (unless otherwise noted). l = 0.33 h pife25201b ? c out = 47 f 0603, c in = 4.7 f 0603 figure 10. efficiency vs i load and v in v out = 1.15 v figure 11. efficiency vs i load and temperature v out = 1.15 v figure 12. v out accuracy vs i load and v in v out = 1.15 v figure 13. v out accuracy vs v in and temperature, v out = 1.15 v figure 14. v out accuracy vs i load and v in v out = 0.60 v figure 15. v out accuracy vs i load and v in v out = 1.50 v
NCP6336 http://onsemi.com 9 typical operating characteristics av in = pv in = 3.6 v, t j = +25 c, dcdc = 1.15 v, ipeak = 3.9 a (unless otherwise noted). l = 0.33 h pife25201b ? c out = 47 f 0603, c in = 4.7 f 0603 figure 16. hss r on vs v in and temperature figure 17. lss r on vs v in and temperature figure 18. i off vs v in and temperature figure 19. i sleep vs v in and temperature figure 20. i q pfm vs v in and temperature figure 21. i q pwm vs v in and temperature
NCP6336 http://onsemi.com 10 typical operating characteristics av in = pv in = 3.6 v, t j = +25 c, dcdc = 1.15 v, ipeak = 3.9 a (unless otherwise noted). l = 0.33 h pife25201b ? c out = 47 f 0603, c in = 4.7 f 0603 figure 22. switchover point v out = 1.15 v figure 23. switchover point v out = 1.50 v figure 24. pwm ripple figure 25. pfm ripple figure 26. normal power up, v out = 1.15 v
NCP6336 http://onsemi.com 11 typical operating characteristics av in = pv in = 3.6 v, t j = +25 c, dcdc = 1.15 v, ipeak = 3.9 a (unless otherwise noted). l = 0.33 h pife25201b ? c out = 47 f 0603, c in = 4.7 f 0603 figure 27. transient load 0.2 to 1.5 a transient line 3.9 ? 3.3 v auto mode figure 28. transient load 0.2 to 1.5 a transient line 3.3 ? 3.9 v auto mode figure 29. transient load 0.01 to 1.3 a auto mode figure 30. transient load 0.1 to 1.4 a auto mode figure 31. transient load 4 to 5.3 a auto mode figure 32. transient load 0 ma ? 600 ma to 1.3 a ? 1.9 a auto mode
NCP6336 http://onsemi.com 12 detailed operating description detailed descriptions the NCP6336 is voltage mode stand?alone synchronous dc to dc converter optimized to supply different sub systems of portable applications powered by one cell li?ion or three cells alkaline/nicd/nimh. the ic can deliver up to 5 a at an i 2 c selectable voltage ranging from 0.6 v to 1.50 v. it can share the same output rail with another dc to dc converter and works as a transient load helper without sinking current on shared rail. a 3 mhz switching frequency allows the use of smaller output filter components. synchronous rectification and automatic pwm/pfm transitions improve overall solution efficiency. forced pwm is also configurable. operating modes, configuration, and output power can be easily selected either by using digital i/o pins or by programming a set of registers using an i 2 c compatible interface capable of operation up to 3.4 mhz. default i 2 c settings are factory programmable. dc to dc converter operation the converter is a synchronous rectifier type with both high side and low side integrated switches. neither external transistor nor diodes are required for NCP6336 operation. feedback and compensation network are also fully integrated. the converter can operate in two different modes: pwm and pfm. the transition between pwm/pfm modes can occur automatically or the switcher can be placed in forced pwm mode by i 2 c programming (pwmvsel0 / pwmvsel1 bits of command register). pwm (pulse width modulation) operating mode in medium and high load conditions, NCP6336 operates in pwm mode from a fixed clock and adapts its duty cycle to regulate the desired output voltage. in this mode, the inductor current is in ccm (continuous current mode) and the voltage is regulated by pwm. the internal n?mosfet switch operates as synchronous rectifier and is driven complementary to the p?mosfet switch. in ccm, the lower switch (n?mosfet) in a synchronous converter provides a lower voltage drop than the diode in an asynchronous converter, which provides less loss and higher efficiency. pfm (pulse frequency modulation) operating mode in order to save power and improve ef ficiency at low loads the NCP6336 operates in pfm mode as the inductor current drops into dcm (discontinuous current mode). the upper fet on time is kept constant and the switching frequency is variable. output voltage is regulated by varying the switching frequency which becomes proportional to loading current. as it does in pwm mode, the internal n?mosfet operates as synchronous rectifier after each p?mosfet on?pulse. when load increases and current in inductor becomes continuous again, the controller automatically turns back to pwm mode. forced pwm the NCP6336 can be programmed to only use pwm and disable the transition to pfm if so desired. output stage NCP6336 is a 3.5 a to 5.0 a output current capable integrated dc to dc converter. to supply such a high current, the internal mosfets need to be large. inductor peak current limitation during normal operation, peak current limitation will monitor and limit the current through the inductor. this current limitation is particularly useful when size and/or height constrain inductor power. the user can select peak current to keep inductor within its specifications. the peak current can be set by writing ipeak[1..0] bits in limconf register. table 1. ipeak values ipeak[1..0] inductor peak current (a) 00 5.2 ? for 3.5 output current 01 5.8 ? for 4.0 output current 10 6.2 ? for 4.5 output current 11 6.8 ? for 5.0 output current output voltage output voltage is set internally by integrated resistor bridge and error amplifier that drives the pwm/pfm controller. no extra component is needed to set output voltage. however, writing in the voutvsel0[6..0] bits of the progvsel0 register or voutvsel1[6..0] bits of the progvsel1 register will change settings. output voltage level can be programmed in the 0.6 v to 1.5 v range by 10 mv steps. the vsel pin and vselgt bit will determine which register between progvsel0 and progvsel1 will set the output voltage. ? if vselgt = 1 and vsel=0 output voltage is set by voutvsel0[6..0] bits (progvsel0 register) ? else output voltage is set by voutvsel1[6..0] bits (progvsel1 register) under voltage lock out (uvlo) NCP6336 core does not operate for voltages below the under voltage lock out (uvlo) level. below uvlo threshold, all internal circuitry (both analog and digital) is held in reset. NCP6336 operation is guaranteed down to v uvlo when battery voltage is dropping off. to avoid erratic on / off behavior, a maximum 200 mv hysteresis is implemented. restart is guaranteed at 2.5 v when vbat voltage is recovering or rising.
NCP6336 http://onsemi.com 13 thermal management thermal shutdown (tsd ) the thermal capability of ic can be exceeded due to step down converter output stage power level. a thermal protection circuitry is therefore implemented to prevent the ic from damage. this protection circuitry is only activated when the core is in active mode (output voltage is turned on). during thermal shut down, output voltage is turned off. when NCP6336 returns from thermal shutdown, it can re?start in 2 different configurations depending on rearm bit in the limconf register (see register description section): ? if rearm = 0 then NCP6336 does not re?start after tsd. to restart, an en pin toggle is required. ? if rearm = 1, NCP6336 re?starts with register values set prior to thermal shutdown. a thermal shut down interrupt is raised upon this event. thermal shut down threshold is set at 150 c (typical) when the die temperature increases and, in order to avoid erratic on / off behavior, a 30 c hysteresis is implemented. after a typical 150 c thermal shut down, NCP6336 will resume to normal operation when the die temperature cools to 120 c. t hermal warnings in addition to the tsd, the die temperature monitoring will flag potential die over temperature. a thermal warning and thermal pre?warning sensor and interrupts are implemented. these can inform the processor that NCP6336 is closed to its thermal shutdown, so preventive measures to cool down die temperature can be taken by software. the warning threshold is set by hardware to 135 c typical when the die temperature increases. the pre?warning threshold is set by default to 105 c, but can be changed by user by setting the tpwth[1..0] bits in the limconf register. active output discharge to make sure that no residual voltage remains in the power supply rail when disabled, an active discharge path can ground the NCP6336 output voltage. for maximum flexibility, this feature can be easily disabled or enabled with dischg bit in pgood register. by default the discharge path is enabled. however the discharged path is activated during the first 100 s after battery insertion. enabling the en pin controls NCP6336 start up. en pin low to high transition starts the power up sequencer. if en is made low, the dc to dc converter is turned off and device enters: ? in sleep mode if sleep_mode i 2 c bit is high or vsel is high, ? in off mode if sleep_mode i 2 c bit and vsel are low. when en pin is set to a high level, the dc to dc converter can be enabled / disabled by writing the envsel0 or envsel1 bit of the progvsel0 and progvsel1 registers: if enx i 2 c bit is high, dc to dc converter is activated, if enx i 2 c is low the dc to dc converter is turned off and device enters in sleep mode a built in pull down resistor disables the device when this pin is left unconnected or not driven. en pin activity does not generate any digital reset. power up sequence (pus) in order to power up the circuit, the input voltage avin has to rise above the vuvlo threshold. this triggers the internal core circuitry power up which is the ?wake up time? (including ?bias time?). this delay is internal and cannot be bypassed. en pin transition within this delay corresponds to the ?initial power up sequence? (ipus): por uvlo avin en wake up time delay[2..0] ~ 750 us 32 us vout dvs ramp time init time ????? ????? figure 33. initial power up sequence in addition a user programmable delay will also take place between end of core circuitry turn on (wake up time and bias time) and init time: the delay[2..0] bits of time register will set this user programmable delay with a 2 ms resolution. with default delay of 0 ms, the NCP6336 ipus takes roughly 900 s, means dc to dc converter output voltage will be ready within 1 ms. the power up output voltage is defined by vsel state. note: during the wake up time, the i 2 c interface is not active. any i 2 c request to the ic during this time period will result in a nack reply. normal, quick and fast power up sequence the previous description applies only when the en transitions during the internal core circuitry power up (wake up and calibration time). otherwise 3 different cases are possible: ? enabling the part by setting en pin from off mode will result in ?normal power up sequence? (npus, with delay;[2..0]). ? enabling the part by setting en pin from sleep mode will result in ?quick power up sequence? (qpus, with delay;[2..0]).
NCP6336 http://onsemi.com 14 ? enabling the dc to dc converter, whereas en is already high, either by setting envsel0 or envsel1 bits or by vsel pin transition will results in ?fast power up sequence? (fpus, without delay[2..0]). sleep mode is when vsel is high and en low, or when sleep_mode i 2 c bit is set and en is low, or finally when dc to dc converter is off and en high. o f f m o d e por uvlo en delay[2..0] 32 us dvs ramp time init time t ftr 20 us bias time avin vout figure 34. normal power up sequence s l e e p m o d e por uvlo avin en delay[2..0] 32 us vout dvs ramp time init time t ftr figure 35. quick power up sequence s l e e p m o d e por uvlo avin vsel 32 us vout dvs ramp time init time t ftr figure 36. fast power up sequence in addition the delay set in delay[2..0] bits in time register will apply only for the en pins turn on sequence (npus and qpus). the power up output voltage is defined by vsel state. note that the sleep mode needs about 150 s to be established. dc to dc converter shut down when shutting down the device, no shut down sequence is required. output voltage is disabled and, depending on the dischg bit state of pgood register, output may be discharged. dc to dc converter shutdown is initiated by either grounding the en pin (hardware shutdown) or, depending on the vsel internal signal level, by clearing the envsel0 or envsel1 bits (software shutdown) in progvsel0 or progvsel1 registers. in hardware shutdown (en = 0), the internal core is still active and i 2 c accessible. NCP6336 shuts internal core down when avin falls below uvlo. dynamic voltage scaling (dvs) this converter supports dynamic voltage scaling (dvs) allowing the output voltage to be reprogrammed via i 2 c commands and provides the different voltages required by the processor. the change between set points is managed in a smooth fashion without disturbing the operation of the processor. when programming a higher voltage, output raises with controlled dv/dt defined by dvs[1..0] bits in time register. when programming a lower voltage the output voltage will decrease accordingly. the dvs step is fixed and the speed is programmable. dvs sequence is automatically initiated by changing output voltage settings. there are two ways to change these settings: ? directly change the active setting register value (voutvsel0[6..0] of progvsel0 register or voutvsel1[6..0] of the progvsel1 register) via i 2 c command ? change the vsel internal signal level by toggling vsel pin. the second method eliminates the i 2 c latency and is therefore faster. the dvs transition mode can be changed with the dvsmode bit in command register: ? in forced pwm mode when accurate output voltage control is needed. v2 v1 internal r eference output voltage t v figure 37. dvs in forced pwm mode diagram ? in auto mode when output voltage has not to be discharged. note that approximately 30 s is needed to transition from pfm mode to pwm mode.
NCP6336 http://onsemi.com 15 v2 v1 internal reference output voltage t v figure 38. dvs in auto mode diagram digital io settings vsel pin by changing vsel pin levels, the user has a latency free way to change NCP6336 configuration: operating mode (auto or pwm forced), the output voltage as well as enable. table 2. vsel pin parameters parameter vsel pin can set register vsel = low register vsel = high enable envsel0 progvsel0[7] envsel1 progvsel1[7] vout voutvsel0[6..0] voutvsel1[6..0] operating mode (auto / pwm forced) pwmvsel0 command[7] pwmvsel1 command[6] vsel pin action can be masked by writing 0 to the vselgt bit in the command register. in that case i 2 c bit corresponding to vsel high will be taken into account. en pin the en pin can be gated by writing the envsel0 or envsel1 bits of the progvsel0 and progvsel1 registers, depending on which register is activated by the vsel internal signal. power good pin (optional) to indicate the output voltage level is established, a power good signal is available. the power good signal is low when the dc to dc converter is off. once the output voltage reaches 95% of the expected o utput level, the power good logic signal becomes high and the open drain output becomes high impedance. during operation when the output drops below 90% of the programmed level the power good logic signal goes low (and the open drain signal transitions to a low impedance state) which indicates a power failure. when the voltage rises again to above 95% the power good signal goes high again. during a positive dvs sequence, when target voltage is higher than initial voltage, the power good logic signal will be set low during output voltage ramping and transition to high once the output voltage reaches 95% of the target voltage. when the target voltage is lower than the initial voltage, power good pin will remain at high level during transition. power good signal during normal operation can be disabled by clearing the pgdcdc bit in pgood register. power good operation during dvs can be controlled by setting / clearing the bit pgdvs in pgood register dcdc_en 32 us min dcdc 95% 90% 3.5 ? 14 us 3.5 ? 14 us 3.5 us pg figure 39. power good signal power good delay in order to generate a reset signal, a delay can be programmed between the output voltage gets 95% of its final value and power good pin is released to high level. the delay is set from 0 ms to 64 ms through the t or[1..0] bits in the time register. the default delay is 0 ms. vout pg delay programmed in tor [2: 0] no tor[ 2:0 ] delay figure 40. power good operation interrupt pin (optional) the interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected (dual edge monitoring). table 3. interrupt sources interrupt name description tsd thermal shut down twarn thermal warning tprew thermal pre warning uvlo under voltage lock out idcdc dc to dc converter current over / below limit pg power good individual bits generating interrupts will be set to 1 in the int_ack register (i 2 c read only registers), indicating the interrupt source. int_ack register is automatically reset by an i 2 c read. the int_sen register (read only register) contains real time indicators of interrupt sources. all interrupt sources can be masked by writing in register int_msk. masked sources will never generate an interrupt request on intb pin.
NCP6336 http://onsemi.com 16 the intb pin is an open drain output. a non masked interrupt request will result in intb pin being driven low. when the host reads the int_ack registers the intb pin is released to high impedance and the interrupt register int_ack is cleared. figure 41 is uvlo event example: intb pin with int_sen/int_msk/int_ack and an i 2 c read access behavior. read i c access on int _ack read read read intb ack_uvlo mask_uvlo sen_uvlo uvlo figure 41. interrupt operation example int_msk register is set to disable intb feature by default. configurations default output voltages, enables, dcdc modes, current limit and other parameters can be factory programmed upon request. below is the default configurations pre?defined: configuration NCP6336 ? 5.0 a default i 2 c address pid product identification rid revision identification fid feature identification 0x1c 14h xxh 00h default vout ? vsel=1 1.15 v default vout ? vsel=0 1.15 v default mode ? vsel=1 auto mode ? on default mode ? vsel=0 auto mode ? on default ipeak 6.8 a opn NCP6336fcct1g marking 6336
NCP6336 http://onsemi.com 17 i 2 c compatible interface NCP6336 can support a subset of i 2 c protocol detailed below. i 2 c communication description start ic address 1 1 read ack data 1 ack data n /ack stop start ack ic address 0 0 write data 1 ack data n ack /ack stop from mcu to ncpxxxx from ncpxxxx to mcu read out from part write inside part figure 42. general protocol description if part does not acknowledge, the /nack will be followed by a stop or sr. if part acknowledges, the ack can be followed by another data or stop or sr the first byte transmitted is the chip address (with the lsb bit set to 1 for a read operation, or set to 0 for a w rite operation). the following data will be: ? in case of a write operation, the register address (@reg) pointing to the register we want to write in followed by the data we will write in that location. the writing process is auto?incremental, so the first data will be written in @reg, the contents of @reg are incremented and the next data byte is placed in the location pointed to by @reg + 1 , etc. ? in case of read operation, the NCP6336 will output the data from the last register that has been accessed by the last write operation. like the writing process, the reading process is auto?incremental. read out from part the master will first make a ?pseudo write? transaction with no data to set the internal address register. then, a stop then start or a repeated start will initiate the read transaction from the register address the initial write transaction has pointe d to: stop ic address 1 1 read ack start ic address 0 0 write register address ack start ack data 1 data n ack /ack stop sets internal register pointer register address value register address + (n?1) n registers read from mcu to ncpxxxx from ncpxxxx to mcu figure 43. read out from part value the first write sequence will set the internal pointer to the register we want access to. then the read transaction will start at the address the write transaction has initiated.
NCP6336 http://onsemi.com 18 transaction with real write then read with stop then start reg + (n ? 1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu ic address 0 0 write ack register reg0 address ack reg value ack sets internal register pointer write value in register reg0 write value in register reg0 + (n?1) n registers write ic address 1 1 read start ack data 1 data k ack /ack stop register reg + (n?1) value register address + (n?1) + k registers read start figure 44. write followed by read transaction (k?1) value write in part write operation will be achieved by only one transaction. after chip address, the mcu first data will be the internal register we want access to, then following data will be the data we want to write in reg, reg + 1, reg + 2, , reg +n. write n registers: reg + (n?1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu start ic address 0 0 write ack register reg0 address ack reg value ack sets internal register pointer write value in register reg0 write value in register reg0 + (n?1) n registers write figure 45. write in n registers i 2 c address NCP6336 has four available i 2 c address selectable by factory settings (add0 to add3). different address settings can be generated upon request to on semiconductor. the default address is set to 38h / 39h since the NCP6336 supports 7?bit address only and ignores a0. table 4. i 2 c address i 2 c address hex a7 a6 a5 a4 a3 a2 a1 a0 add0 w 0x20 r 0x21 0 0 1 0 0 0 0 r/w add 0x10 ? add1 w 0x28 r 0x29 0 0 1 0 1 0 0 r/w add 0x14 ? add2 w 0x30 r 0x31 0 0 1 1 0 0 0 r/w add 0x18 ? add3 (default) w 0x38 r 0x39 0 0 1 1 1 0 0 r/w add 0x1c ?
NCP6336 http://onsemi.com 19 register map table 5 describes i 2 c registers. registers / bits can be: r read only register rc read then clear rw read and write register reserved address is reserved and register/bit is not physically designed spare address is reserved and register/bit is physically designed table 5. i 2 c registers map 5 a configuration (NCP6336) add. register name type def. function 00h int_ack rc 00h interrupt register 01h int_sen r 00h sense register (real time status) 02h int_msk rw ffh mask register to enable or disable interrupt sources (trim) 03h pid r 14h product identification 04h rid r metal revision identification 05h fid r 00h features identification (trim) 06h to 0fh ? ? ? reserved for future use 10h progvsel1 rw b7h output voltage settings and en for vsel pin = high (trim) 11h progvsel0 rw b7h output voltage settings and en for vsel pin = low (trim) 12h pgood rw 10h power good and active discharge settings (trim) 13h time rw 09h enabling and dvs timings (trim) 14h command rw 01h enabling and operating mode command register (trim) 15h module rw 80h active module count settings (test) 16h limconf rw e3h reset and limit configuration register (trim) 17h to 1fh ? ? ? reserved for future use 20h to ffh ? ? ? reserved. test registers
NCP6336 http://onsemi.com 20 registers description table 6. interrupt acknowledge register name: intack address: 00h type: rc default: 00000000b (00h) trigger: dual edge [d7..d0] d7 d6 d5 d4 d3 d2 d1 d0 ack_tsd ack_twarn ack_tprew spare = 0 spare = 0 ack_uvlo ack_idcdc ack_pg bit bit description ack_pg power good sense acknowledgement 0: cleared 1: dcdc power good event detected ack_idcdc dcdc over current sense acknowledgement 0: cleared 1: dcdc over current event detected ack_uvlo under voltage sense acknowledgement 0: cleared 1: under voltage event detected ack_tprew thermal pre warning sense acknowledgement 0: cleared 1: thermal pre warning event detected ack_twarn thermal warning sense acknowledgement 0: cleared 1: thermal warning event detected ack_tsd thermal shutdown sense acknowledgement 0: cleared 1: thermal shutdown event detected table 7. interrupt sense register name: intsen address: 01h type: r default: 00000000b (00h) trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 sen_tsd sen_twarn sen_tprew spare = 0 spare = 0 sen_uvlo sen_idcdc sen_pg bit bit description sen_pg power good sense 0: dcdc output voltage below target 1: dcdc output voltage within nominal range sen _idcdc dcdc over current sense 0: dcdc output current is below limit 1: dcdc output current is over limit sen _uvlo under voltage sense 0: input voltage higher than uvlo threshold 1: input voltage lower than uvlo threshold sen _tprew thermal pre warning sense 0: junction temperature below thermal pre?warning limit 1: junction temperature over thermal pre?warning limit sen _twarn thermal warning sense 0: junction temperature below thermal warning limit 1: junction temperature over thermal warning limit sen _tsd thermal shutdown sense 0: junction temperature below thermal shutdown limit 1: junction temperature over thermal shutdown limit
NCP6336 http://onsemi.com 21 table 8. interrupt mask register name: intmask address: 02h type: rw default: see register map trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 mask_tsd mask_twarn mask_tprew spare = 1 spare = 1 mask_uvlo mask_idcdc mask_pg bit bit description mask_pg power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask _idcdc dcdc over current interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask _uvlo under voltage interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask _tprew thermal pre warning interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask _twarn thermal warning interrupt source mask 0: interrupt is enabled 1: interrupt is masked mask _tsd thermal shutdown interrupt source mask 0: interrupt is enabled 1: interrupt is masked table 9. product id register name: pid address: 03h type: r default: 00010100b (14h) trigger: n/a reset on n/a d7 d6 d5 d4 d3 d2 d1 d0 pid_7 pid_6 pid_5 pid_4 pid_3 pid_2 pid_1 pid_0 table 10. revision id register name: rid address: 04h type: r default: metal trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 rid_7 rid_6 rid_5 rid_4 rid_3 rid_2 rid_1 rid_0 bit bit description rid[7..0] revision identification 00000000: first silicon
NCP6336 http://onsemi.com 22 table 11. feature id register name: fid address: 05h type: r default: see register map trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 spare spare spare spare fid_3 fid_2 fid_1 fid_0 bit bit description fid[3..0] feature identification 00000000: NCP6336 5.0 a configuration table 12. dc to dc voltage prog (vsel = 1) register name: progvsel1 address: 10h type: rw default: see register map trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 envsel1 voutvsel1[6..0] bit bit description voutvsel1[6..0] sets the dc to dc converter output voltage when vsel pin = 1 and vsel pin function is enabled in register command.d0, or when vsel pin function is disabled in register command.d0 0000000b = 600 mv ? 1011010b = 1500 mv (steps of 10 mv) 1011011b to 1111111b reserved envsel1 en pin gating for vsel internal signal = high 0: disabled 1: enabled table 13. dc to dc voltage prog (vsel = 0) register name: progvsel0 address: 11h type: rw default: see register map trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 envsel0 voutvsel0[6..0] bit bit description voutvsel0[6..0] sets the dc to dc converter output voltage when vsel pin = 0 and vsel pin function is enabled in register command.d0 0000000b = 600 mv ? 1011010b = 1500 mv (steps of 10 mv) 1011011b to 1111111b reserved envsel0 en pin gating for vsel internal signal = low 0: disabled 1: enabled
NCP6336 http://onsemi.com 23 table 14. power good register name: pgood address: 12h type: rw default: see register map trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare = 0 dischg tor[1..0] pgdvs pgdcdc bit bit description pgdcdc power good enabling 0 = disabled 1 = enabled pgdvs power good active on dvs 0 = disabled 1 = enabled tor[1..0] time out reset settings for power good 00 = 0 ms 01 = 8 ms 10 = 32 ms 11 = 64 ms dischg active discharge bit enabling 0 = discharge path disabled 1 = discharge path enabled table 15. timing register name: time address: 13h type: rw default: see register map trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 delay[2..0] dvs[1..0] spare = 0 dbn_time[1..0] bit bit description dbn_time[1..0] en and vsel debounce time 00 = no debounce 01 = 1?2 s 10 = 2?3 s 11 = 3?4 s dvs[1..0] dvs speed 00 = 10 mv step / 0.333 s 01 = 10 mv step / 0.666 s 10 = 10 mv step / 1.333 s 11 = 10 mv step / 2.666 s delay[2..0] delay applied upon enabling (ms) 000b = 0 ms ? 111b = 14 ms (steps of 2 ms)
NCP6336 http://onsemi.com 24 table 16. command register name: command address: 14h type: rw default: see register map trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 pwmvsel0 pwmvsel1 dvsmode sleep_mode spare = 0 spare = 0 spare = 0 vselgt bit bit description vselgt vsel pin gating 0 = disabled 1 = enabled sleep_mode sleep mode 0 = low iq mode when en and vsel low 1 = force product in sleep mode (when en and vsel are low) dvsmode dvs transition mode selection 0 = auto 1 = forced pwm pwmvsel1 operating mode for vsel internal signal = high 0 = auto 1 = forced pwm pwmvsel0 operating mode for vsel internal signal = low 0 = auto 1 = forced pwm table 17. output stage module settings register name: module address: 15h type: rw default: 10000000b (80h) trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 modul[3..0] spare = 0 spare = 0 spare = 0 spare = 0 bit bit description modul [3..0] number of modules 0000 = 1 module 0001 = 2 modules 0010 ~ 1111 = 9 modules
NCP6336 http://onsemi.com 25 table 18. limits configuration register name: limconf adress: 16h type: rw default: see register map trigger: n/a d7 d6 d5 d4 d3 d2 d1 d0 ipeak[1..0] tpwth[1..0] spare = 0 spare = 0 rststatus rearm bit bit description rearm rearming of device after tsd 0: no re?arming after tsd 1: re?arming active after tsd with no reset of i 2 c registers: new power?up sequence is initiated with previously programmed i 2 c registers values rststatus reset indicator bit 0: must be written to 0 after register reset 1: default (loaded after registers reset) tpwth[1..0] thermal pre?warning threshold settings 00 = 83 c 01 = 94 c 10 = 105 c 11 = 116 c ipeak inductor peak current settings 00 = 5.2 a (for 3.5 a output current) 01 = 5.8 a (for 4.0 a output current) 10 = 6.2 a (for 4.5 a output current) 11 = 6.8 a (for 5.0 a output current)
NCP6336 http://onsemi.com 26 application information figure 46. typical application schematic 330 nh 47 uf processor core NCP6336 i c thermal protection processor i c control interface operating mode control output monitoring voltage selection interrupt power fail dcdc 5a supply input dcdc 3mhz controller sense enable control input 4.7 uf sda scl agnd pgnd intb pgnd pg vsel en core sw pvin pgnd fb d2 e1 b4 a2 a1 b3 b2 b1 a3 d3 d4 e3 e4 c1 c2 c3 c4 a4 e2 d1 avin output filter design considerations the output filter introduces a double pole in the system at a frequency of: f lc 1 2 l c (eq. 1) the NCP6336 internal compensation network is optimized for a typical output filter comprising a 330 nh inductor and 47 f capacitor as described in the basic application schematic shown in figure 46. voltage sensing considerations in order to regulate power supply rail, NCP6336 should sense its output voltage. thanks to the fb pin, the ic can support two sensing methods: ? normal case: the voltage sensing is achieved close to the output capacitor. in that case, fb is connected to the output capacitor positive terminal (voltage to regulate). ? remote sensing: in remote sensing, the power supply rail sense is made close to the system powered by the NCP6336. the voltage to system is more accurate, since pcb line impedance voltage drop is within the regulation loop. in that case, we recommend connecting the fb pin to the system decoupling capacitor positive terminal. components selection inductor selection the inductance of the inductor is determined by given peak?to?peak ripple current i l_pp of approximately 20% to 50% of the maximum output current i out_max for a trade?off between transient response and output ripple. the inductance corresponding to the given current ripple is: l v in v out v out v in f sw i l_pp (eq. 2) the selected inductor must have high enough saturation current rating to be higher than the maximum peak current that is i l_max i out_max i l_pp 2 (eq. 3) the inductor also needs to have high enough current rating based on temperature rise concern. low dcr is good for efficiency improvement and temperature rise reduction. table 19 shows recommended.
NCP6336 http://onsemi.com 27 table 19. inductor selection supplier part # value ( h) size (mm) (l x l x t) (mm) saturation current max (a) dcr max at 25 c (m ) cyntec pife20161b?r33ms?11 0.33 2.0 x 1.6 x 1.2 4.0 33 cyntec pife25201b?r33ms?11 0.33 2.5 x 2.0 x 1.2 5.2 17 cyntec pife32251b?r33ms?11 0.33 3.2 x 2.5 x 1.2 6.5 14 toko dfe201612p?h?r30m 0.30 2.0 x 1.6 x 1.2 4.8 29 toko dfe252012p?h?r33m 0.33 2.5 x 2.0 x 1.2 5.2 24 toko fdsd0412?h?r33m 0.33 4.2 x 4.2 x 1.2 7.5 19 tdk vls252012hbx?r33m 0.33 2.5 x 2.0 x 1.2 5.3 25 tdk spm5030t?r35m 0.35 7.1 x 6.5 x 3.0 14.9 4 output capacitor selection the output capacitor selection is determined by output voltage ripple and load transient response requirement. for high transient load performance high output capacitor value must be used. for a given peak?to?peak ripple current i l_pp in the inductor of the output filter, the output voltage ripple across the output capacitor is the sum of three components as below. v out_pp
v out_pp(c) v out_pp(esr) v out_pp(esl) , (eq. 4) where v out_pp(c) is a ripple component by an equivalent total capacitance of the output capacitors, v out_pp(esr) is a ripple component by an equivalent esr of the output capacitors, and v out_pp(esl) is a ripple component by an equivalent esl of the output capacitors. in pwm operation mode, the three ripple components can be obtained by v out_pp(c) i l_pp 8 c f sw , (eq. 5) and v out_pp(esr) i l_pp esr (eq. 6) v out_pp(esl) esl esl l v in (eq. 7) and the peak?to?peak ripple current is i l_pp v in v out v out v in f sw l (eq. 8) in applications with all ceramic output capacitors, the main ripple component of the output ripple is v out_pp(c) . so that the minimum output capacitance can be calculated regarding to a given output ripple requirement v out_pp in pwm operation mode. c min i l_pp 8 v out_pp f sw (eq. 9) input capacitor selection one of the input capacitor selection guides is the input voltage ripple requirement. to minimize the input voltage ripple and get better decoupling in the input power supply rail, ceramic capacitor is recommended due to low esr and esl. the minimum input capacitance regarding to the input ripple voltage v in_pp is c in_min i out_max d d 2 v in_pp f sw (eq. 10) where d v out v in (eq. 11) in addition, the input capacitor needs to be able to absorb the input current, which has a rms value of i in_rms i out_max d d 2 (eq. 12) the input capacitor also needs to be sufficient to protect the device from over voltage spike, and normally at least 4.7 f capacitor is required. the input capacitor should be located as close as possible to the ic. all pgnds are connected together to the ground terminal of the input cap which then connects to the ground plane. all pvin are connected together to the vbat terminal of the input cap which then connects to the vbat plane. electrical layout considerations good electrical layout is a key to ensuring proper operation, high efficiency, and noise reduction. electrical layout guidelines are: ? use wide and short traces for power paths (such as pvin, vout, sw, and pgnd) to reduce parasitic inductance and high?frequency loop area. it is also good for efficiency improvement. ? the device should be well decoupled by input capacitor and input loop area should be as small as possible to reduce parasitic inductance, input voltage spike, and noise emission. ? sw node should be a large copper, but compact because it is also a noise source.
NCP6336 http://onsemi.com 28 ? it would be good to have separated ground planes for pgnd and agnd and connect the two planes at one point. try best to avoid overlap of input ground loop and output ground loop to prevent noise impact on output regulation. ? arrange a ?quiet? path for output voltage sense, and make it surrounded by a ground plane. thermal layout considerations good pcb layout helps high power dissipation from a small package with reduced temperature rise. thermal layout guidelines are: ? a four or more layers pcb board with solid ground planes is preferred for better heat dissipation. ? more free vias are welcome to be around ic to connect the inner ground layers to reduce thermal impedance. ? use large area copper especially in top layer to help thermal conduction and radiation. ? use two layers for the high current paths (pvin, pgnd, sw) in order to split current in two different paths and limit pcb copper self heating. (see demo board example figure 48) figure 47. layout recommendation 4.2 mm s < 18.00 mm 0603 4.7 uf 2.3 x 1.2 mm 0603 47 uf 2.3 x 1.2 mm 0.33 uh 2.0x1.6 mm pvin avin sw sw pvin pgnd pgnd intb scl en pvin pgnd pgnd sda pgnd pg vsel sw sw pgnd fb agnd 4.3 mm pife2016b pife2016b figure 48. demo board example input capacitor placed as close as possible to the ic. pvin directly connected to cin input capacitor, and then connected to the vin plane. local mini planes used on the top layer (green) and layer just below top layer (yellow) with laser vias. avin connected to the vin plane just after the capacitor. agnd directly connected to the gnd plane. pgnd directly connected to cin input capacitor, and then connected to the gnd plane: local mini planes used on the top layer (green) and layer just below top layer (yellow) with laser vias. sw connected to the lout inductor with local mini planes used on the top layer (green) and layer just below top layer (yellow) with laser vias. legend: in green are top layer planes and wires in yellow are layer1 plane and wires (just below top layer) big circles gray are normal vias small circles gray are top to layer1 vias
NCP6336 http://onsemi.com 29 ordering information device marking configuration package shipping ? NCP6336fcct1g 6336 5 a 1.15 v wlcsp20 2.02 x 1.62 mm (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. demo board available: the NCP6336gevb/d evaluation board that configures the device in typical application to supply constant voltage.
NCP6336 http://onsemi.com 30 package dimensions wlcsp20, 1.62x2.02 case 568ag issue d seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to the spherical crowns of the solder balls. 2x dim a min max ??? millimeters a1 d 1.62 bsc e b 0.24 0.28 e 0.40 bsc 0.60 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 20x b 4 c b a 0.10 c a a1 a2 c 0.17 0.23 2.02 bsc 0.25 20x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.10 c 2x top view side view bottom view note 3 e recommended package outline 123 pitch d e pitch a1 a2 0.33 0.39 e/2 die coat (optional) detail a a2 a3 detail a a3 0.02 0.04 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP6336/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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